This invention relates generally to computer systems, and more particularly, to the architecture of computer systems containing a central processing unit.
Computer systems containing a central processing unit (CPU) are well known in the art. These systems may be found in many common devices such as, but not limited to, calculators, personal organizers, pagers, toys, smart cards, cellular phones, home and office appliances, consumer electronic devices, and the like. An example of one such computer system 400 is shown in FIG. 1. The computer system 400 comprises a CPU 200, one or more peripherals 290, 300, 370, 390, and a universal bus 100. The CPU 200 contains circuitry for reading data and program instruction codes, decoding the instructions, and performing operations on the data according to the instructions. These operations may include steps such as, for example, moving data between peripherals and/or memory, performing mathematical operations, or making logical decisions based on the data. The peripherals 290, 300, 370, 390 may include devices such as modems, memory controllers, encryption engines, timers, input/output device controllers, and the like. Although four peripherals and one CPU are shown in the example of FIG. 1, it will be appreciated by those of ordinary skill that any number of CPUs and peripherals may be present in such computer systems. As is known, the CPU and peripherals of the computer system 400 may be organized into bus slaves and bus masters. A bus master is a device that takes control of the universal bus 100 to read data from or write data to the bus. A bus slave is a device that does not control the flow of information on the universal bus 100. Instead, it sends or receives data on the bus only in response to a request from a bus master. In accordance with the embodiment of FIG. 1, and by way of example, the CPU 200 and the peripheral 290 are bus masters, the peripherals 300, 370, 390 are bus slaves.
As is well understood, the universal bus 100 is a set of component buses that are used to transfer data between bus masters 200, 290 and bus slaves 300, 370, 390. The component buses comprise a universal control bus 102, a universal feedback bus 101, a universal address bus 103, and a universal data bus 104. The universal bus 100 can include any multiplexing, 3-stating, or decoding logic necessary to route the signals between the plurality of bus masters 200, 290 and the plurality of bus slaves 300, 370, 390.
The universal control bus 102 is used by the bus masters 200, 290 to communicate read and write signals to bus slaves 300, 370, 390. A read signal consists of data flowing from a bus slave 300, 370, 390 to a bus master 200, 290. A write signal consists of data flowing from a bus master to a bus slave. The universal control bus 102 is also used by the bus masters 200, 290 to request control of the bus, since only one bus master can be in control of the bus at any time. When multiple bus masters request control of the universal bus at the same time, a peripheral frequently referred to as a universal bus arbiter 390, mediates the various requests for control and selects a device via well known and equivalent arbitration schemes.
The universal feedback bus 101 is used by the bus slaves 300, 370, 390 to inform the bus masters 200, 290 that a read or write operation has been completed. The universal feedback bus 101 is also used by the universal bus arbiter 390 to grant control of the universal bus 100 to a particular requesting bus master.
The universal address bus 103 is used by the bus masters 200, 290 to select a particular register of a bus slave 300, 370, 390 or word in a memory module for read and write operations. The set of locations that can be addressed by the universal address bus 103 is called the address space of the computer system. Each location in the address space is assigned a numerical address. The locations within the address space are selected by applying the numerical addresses to physical address lines of the universal bus 103. The relationship between the addresses that refer to the locations in the address space and the blocks of memory associated with each peripheral in the address space is called the system memory map.
FIG. 2 shows a memory map 960 for the computer system 400 of FIG. 1. As seen from the memory map 960, an address space 950 for the computer system 400 comprises a block of memory addresses (951, 953, 955) for peripherals 300, 370, and 390 respectively. Also shown in FIG. 2 are examples of addresses that are applied to the universal address bus 103 physical address lines to select locations within the address space. Each of the universal bus 100 addresses can be split into two sections; one section selects the block of the memory map 960 for a particular peripheral, for example, the address section 961 selects the block 951 for peripheral 300; the other section selects a particular register inside the selected memory block, for example the address section 962 selects the register 952 in the block 951.
Referring back to FIG. 1, the universal data bus 104 is used by a bus master 200, 290 when it writes data to a bus slave 300, 370, 390, and is used by a bus slave 300, 370, 390 when a bus master 200, 290 reads data from the bus slave 300, 370, 390. In some computer systems, the universal data bus is a bi-directional bus that is used for both reading and writing data. In other computer systems the universal data bus 104 can be partitioned into two buses, a universal read data bus that propagates read data from the bus slaves 300, 370, 390 to the bus masters 200, 290 and a universal write data bus that propagates the write data from the bus masters 200, 290 to the bus slaves 300, 370, 390.
The central processing unit (CPU) 200 comprises a group of registers and operation units integrated together in a unitary instruction set architecture. The instruction set architecture is characterized by a set of instruction codes and the sequences of control signals generated by decoding the instruction codes, that operate on the registers and operation units in the central processing unit 200 to execute those instruction codes. In general, the CPU 200 sequentially processes a series of instruction codes that are read over the universal bus 100 from a peripheral. The processing of each instruction code causes the CPU 200 to perform actions on data contained in the registers or interact with the peripherals over the universal bus 100.
The group of registers of the CPU 200 comprises an instruction register 211, a bank of data registers 220, a bank of address registers 230, a status register 218, and a state register 219. The bank of data registers primarily comprises general purpose data registers 212, 213 that are used to hold data the CPU 200 is performing operations on. The bank of address registers comprises general purpose address registers 214, 215 and program address registers such as a program counter 216 and stack pointer 217.
The CPU 200 further comprises a control unit 250, and a set of operation units 240. The control unit 250 includes a set of control sequences 251-259. Each control sequence generates the control signals necessary to fetch, decode, and execute a particular instruction code. The operation units 241-249 are functions that combine data and address registers in some arithmetic or logical operation specified by the instruction codes.
The registers, control unit 250, and set of operation units 240 are connected by a number of buses that carry signals within the CPU 200. These buses comprise an instruction bus 201, a next state bus 206, a current state bus 207, a new status bus 203, a status bus 205, an internal control bus 202, and an internal data bus 204. All of these buses carry information in only one direction except for the internal data bus 204. The direction of data flow is indicated by the arrows in FIG. 1. The instruction bus 201 couples the instruction register 211 to the control unit 250. The next state bus 206 and the current state bus 207 connect the control unit 250 to the state register 219. The status bus 205 links the status register 218 to the control unit 250 and the set of operation units 240. The internal control bus carries signals from the control unit 250 to the status register 218, instruction register 211, data registers 220, address registers 230, and the set of operation units 240. The internal data bus 204 couples the set of operation units 240, address registers 230, and data registers 220 for bi-directional signaling.
Generally, the instruction codes that the CPU 200 executes are stored in a section of the address space called the program space. The CPU 200 reads the instruction codes from the program space one at a time. Usually, after executing an instruction code, the CPU 200 reads the instruction code having the next sequential address. The program counter 216 contains the address of the location in the memory map from where the next instruction for the CPU 200 to execute will be read. After the instruction is read, the program counter is incremented by one address. Certain instruction codes will cause the CPU 200 to jump to another address to read the next instruction code to execute. When this happens, the program counter 216 will be modified to reflect the jump in address.
The state register 219 contains the current state of the CPU 200. The current state of the CPU 200 determines which of the set of control sequences 251-259 the CPU 200 is currently executing. For example, when the CPU 200 is reading in the next instruction from a peripheral, it is in the fetch state. The fetch control sequence is executed by the control unit 250. This causes the CPU 200 to place the address currently in the program counter 216 on the universal address bus 103 and to use the universal control bus 102 to signal a read operation. The instruction code at the specified address in the memory map is loaded into the instruction register 211 and the program counter is incremented by one. The instruction code in the instruction register 211 is then loaded into the control unit 250 over the instruction bus 201. The control unit 250 decodes the instruction code and uses it to determine a new state. The new state is loaded over the next state bus 206 into the state register 219. This new state is then used to determine which of the set of control sequences 251-259 to perform. After the CPU 200 performs the actions required by an instruction code, it returns to the fetch state and loads the next instruction code.
Computing systems like the one shown in FIG. 1 can be implemented in many different ways. For example, the CPU 200 and peripherals 290, 300, 370, 390 may comprise separate integrated circuits placed on an electronic circuit board. Alternately, some of the peripherals may be devices other than integrated circuits. As still another alternative, the CPU 200 and one or more peripherals 290, 300, 370, 390 may be combined into a single integrated circuit. Such an integrated circuit containing several devices is referred to as an application specific integrated circuit or ASIC.
The CPU is usually the most expensive part of the computer system 400 of FIG. 1. This is due, in part, to the complexity and size of the CPU circuitry. If the computing device is an ASIC, the size of the CPU portion of the ASIC is directly related to the cost of the ASIC. Also, the CPU is oftentimes the largest power consumer of a computing system and the complexity of the CPU is directly related to power consumption. This is an important issue in portable computing devices that rely on a battery or in devices that derive their power from radio signals such as some smart cards. In these applications, it is important that the CPU be kept as small and simple as possible in order to produce a low cost and low power computing device.
Computer systems designers frequently make use of pre-existing CPUs and peripheral devices when designing new systems. This is especially true of the CPU since CPUs are complicated devices that are expensive to design and change. As seen in FIG. 1, CPUs typically contain numerous data registers 220, address registers 230, functional circuitry 241-249 and control registers 219, 218, 211. Based upon the application, however, a particular computer system may not need all system features and functionality. Because of this, the general purpose CPU used in many modem computer systems is oftentimes more complicated, power-consuming, and expensive than is actually required.
After a computer system has been designed, it is often necessary to modify the computing device to add new peripherals and functions. These modifications will oftentimes result in different requirements for the CPU. If the CPU can not meet these requirements and must be replaced, the cost of redesigning the computer system can be high.
In many applications of computing systems it is desirable to use a computer system for multiple applications that make use of different peripherals. However, many computer systems are manufactured with all of the instruction codes (programming) in ROM so that the computer systems can not be reprogrammed easily. In such computer systems it is impossible to adapt the computer system for the different applications once it has been manufactured.
Based on the forgoing, there is a need for a new computer system architecture; one that employs lower complexity, cost, and power consumption. The architecture should permit peripherals and functions to be added to the computer system without the need for redesign and should support multiple applications without the need for complete reprogramming.